RNS-based implementation of 8×8 point 2D-DCT over field-programmable devices
P. García‐Fernández, A. Lloris · Electronics Letters · 2003
A new implementation of an 8×8 two-dimensional discrete cosine transform (2D-DCT) processor based on the residue number system (RNS) is presented. This architecture makes use of a fast cosine transform algorithm. It is shown that the RNS implementation of the 2D-DCT over field-programmable logic devices leads to a 129% throughput improvement over the equivalent binary system.