4-stage pipeline architecture
A.N. Trivedi · 2002
Pipelined architectures have advantages over conventional processor design. In this paper, using a four-stage pipelining in the architecture of a contemporary processor, the design illustrates a 30% decrease in output of a single task when four tasks are concurrently executed. Throughput of the processor can increase up to 270%. The cost effectivity is enhanced by using a single set of peripherals. Effective comparison of the 4-stage pipelined processor is also presented.>