A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology
Xuemi Zhao, Zhiying Wang, Hongyi Lu, Kui Dai · 2006
In this paper a RSA crypto coprocessor that is fabricated using a 0.18mum CMOS technology is presented. This processor combines a new version of high radix Montgomery multiplication algorithm with a super-pipeline design. With this algorithm, modular exponentiation can be decomposed into a series of primitive operation (PO) matrixes. All the POs are scheduled on the pipeline by employing column-sharing strategy, and inside the PO all the partial results are compressed first by Wallace tree to assure only one carry propagation in the critical path. With these optimizations, a decryption rate of 6.35 Mbps can be achieved for 1024-bit RSA