Parallel-by-Bit Arithmetic Computational Techniques
H.L. Millis · 2005
This paper describes a technique for performing multiple, concurrent, bit serial, r adix 2, sign and magnitude, most significant bit first arithmetic operations (addition, subtraction, multiplication, divide, e tc.) in separate parallel hardware elements. A set of these elements can be programmed to evaluate an algebraic equation by pairing and evaluating its initial arguments in a first set of elements, pairing the results in a next set of elements, and so on until a solution is obtained. Adder/subtractor and mu1 tiplier elements are described which operate on both register held word output digits and the sum and carry digits resulting from other parallel-by-bit arithmetic operations. A divider element is noted and other features of the technique di scussed. The technique offers an off-line arithmetic enhancement capability for conventional g-p computers and could offer, under proper circumstances, a Val id a1 ternative to mu1 tiprocessors for providing additional a rithmetic capability.