System-level modeling and verification: a comprehensive design methodology
Paolo Enrico Camurati, Fulvio Corno, P. Prinetto, C. Bayol, B. Soulas · 2002
Working at system level is attracting increasing interest, as it supports the exploration of several alternatives, before the hardware/software partitioning takes place. New issues must be taken into account, such as validation and verification at all steps. This paper presents a system-level design methodology that supports description, validation, and verification at system-level.>