VLSI architecture design for variable-size block motion estimation in MPEG-4 AVC/H.264
Cao Wei, Zhang Yan, Mao Zhi Gang, Lv Zhi Qiang · 2005
VBSME is adopted in the MPEG-4 AVC/H.264 standard. In this paper, we proposed a new VLSI architecture for VBSME with FS and TSS algorithms to support two resolutions. The architecture can reuse the smaller blocks' SADs to calculate 4.1 motion vectors of a 16 /spl times/ 16 block in parallel. Our design was implemented with 0.25/spl mu/m CMOS technology. Under a clock frequency of 150Mhz, the architecture allows the real-time processing of 352 /spl times/ 288 (or 720 /spl times/ 576) at 30fps with FS (or TSS) in a search range [-16, +15].