SRAM-FPGA implementation of masked S-Box based DPA countermeasure for AES
Najeh Kamoun, Lilian Bossuet, Adel Ghazel · 2008
This paper presents FPGA implementation and overhead evaluation for an algorithmic DPA countermeasure for advanced encryption standard AES. To reduce implementation overhead the masked compact S-Box, proposed by Canright, was chosen to implement a DPA countermeasure on an SRAM FPGA. Obtained results showed that secured AES IP leads to slices number increase by 60,1% and a frequency decrease by 4%.