Multiple core PLC CPU with tight thread synchronization
Adam Milik, Miroslaw Chmiel, Edward Hrynkiewicz · 2016
The paper presents the architecture of PLC CPU consisting of multiple cores enabling parallel processing of control algorithms. Control programs consist of many program fragments that are suitable for parallel execution. Proposed architecture is constructed from independent logic and arithmetic units. They share common data memories of respective types. In order to enable tight coupling of processing a semaphored memory was proposed. This idea combines the memory with semaphore control. The data flow among processors is controlled by semaphored memory that is a part of global memory space. Correctness of the design was verified by FPGA implementation. Architecture is not intended for manual programming. A respective compiler has been developed that outlines are shortly given.