Design of reconfigurable carry select adders
Jin-Fu Li, Yao-Chang Kuo, Chao-Da Huang, Tsu-Wei Tseng, Chin‐Long Wey · 2005
Digital signal processing (DSP) processors for real-time processing of multimedia signals usually include fast reconfrgurable parallel adders for the operations of integers with different precisions. This paper presents a reconfrgurable carry select adder (CSA). High reconfrgurability is achieved with inter-block and intra-block partition schemes. This methodology only causes very small performance penalty and area overhead. Experimental results show that the worst delay ofa 64-bit reconfigurable CSA with eight 8-bit blocks is about 2.4ns based on the TSMC 0.18pm technology. Also, the area overhead ofthe additional partition circuitry is only about 4.6%.