MorphoSys: a reconfigurable architecture for multimedia applications
Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi Kurdahi, Nader Bagherzadeh, Eliseu M. C. Filho · Symposium on Integrated Circuits and Systems Design · 1998
We describe the MorphoSys reconfigurable system, which combines a reconfigurable array of processor cells with a RISC processor core and a high bandwidth memory interface unit. We introduce the array architecture, its configuration memory, inter-connection network, role of the control processor and related components. Architecture implementation is described in brief and the efficacy of MorphoSys is demonstrated through simulation of video compression (MPEG-2) and target-recognition applications. Comparison with other implementations illustrates that MorphoSys achieves higher performance by up to 10X.