Fault modeling and defect level projections in digital ICs
José T. de Sousa, F.M. Gonçalves, João Paulo Teixeira, T.W. Williams · 2002
This paper presents a new model for evaluating the Defect Level, DL, in VLSI circuits as a function of the yield, Y , and the stuck-at fault coverage, T . It is shown that the observed DL(T ) curve can be accurately modeled using non equally probable, realistic faults predicted from defect statistics data and IC layout. The deviation of DL(T ) from the one estimated by the Williams-Brown equation is shown to be caused by two effects. First, the topology of the most likely realistic faults determine their susceptibility, which is typically lower than the stuck-at fault susceptibility. Second, the incompleteness of a given test set and the detection technique (such as static voltage testing) determine a non 100% defect coverage. The suitability of the model was assessed by means of layout fault extraction and switch-level fault simulation, and the results obtained agree with previously published DL(T ) experimental results on actual ICs. 1