Resilient 3D Network-on-Chip Design and Analysis
Pooria M. Yaghini · eScholarship (California Digital Library) · 2016
Like every other major changes in computer architecture, exascale computing, targetedfor 2020, requires dramatic and unanticipated shifts in different perspectives.The biggest challenge facing this trend is to design an exascale system with a hundredfoldoptimization on the estimated power cost of above $2.5B per year for a systemdesigned with current technology. It has been reported that a large portion of totalpower is consumed for communication through interconnection network. Communicationbetween the computational components of System-on-Chip (SoC) designs canaccount for more than 25 percent of the energy dissipation of the whole system. NoCis recognized by many researchers as the best communication infrastructure for manycoresystems. To lower communication power, researchers have proposed the ideaof designing thinned and stacked 3D ICs. 3D ICs, fabricated using Through-SiliconVia (TSV), offer higher bandwidths, smaller form factors, shorter wire lengths, lowerpower, and better performance than traditional 2D ICs. The combination of 3D structuresand NoC is the most promising approach for obtaining the projected performanceand power requirements for exascale systems. Besides the extremely constrained power budget, achieving an acceptable level of resiliency for 1,000,000 cores in an exascalesystem is a crucial challenge. Communication reliability, due to the huge amount ofdata movement in these systems, plays a key role.In this dissertation, the focus is to identify, characterize, and mitigate the reliabilitythreats of TSV-based 3D communication structures, specifically threats introduced byTSV-to-TSV coupling fault.In the first step which is the identification of the reliability threats, the potential physicalfaults of a baseline TSV-based 3D NoC architecture by targeting Two-dimensional(2D) NoC components and their inter-die connections is classified. Subsequently, TSVissues, thermal concerns, and Single Event Effect (SEE) are investigated and categorized,in order to propose evaluation metrics for inspecting the resiliency of 3D NoCdesigns.Then, in the second step, having overviewed the common TSV issues, a frameworkis proposed for quantifying the 3D NoC reliability using formal methods. TSV issuesare modeled as a time-invariant failure probability and a reliability criterion for TSVbasedNoC is defined. The relationship between NoC reliability and TSV failure isquantified. For the first time, the reliability criterion is reduced to a tractable closedformexpression that requires a single Monte Carlo simulation.In the third step, a system-level TSV coupling fault model is proposed, which modelsthe capacitive coupling effect, considering thermal impact, at circuit-level accuracy.This model can be plugged into any system-level and RTL-level TSV-based 3D-ICdata-oriented simulator. Having analyzed and recorded the TSV coupling effect atcircuit-level, these effects are applied to the Through-Silicon Vias (TSVs) dynamically in system-level simulations at runtime through precise monitoring and calculation. Theproposed fault model is potentially useful for evaluating the reliability of 3D many-coreapplications in which TSV coupling may lead to failure.After setting up the TSV coupling fault modeling framework, multiple coding approachesare proposed to prevent coupling fault occurrence on TSV links. In theseapproaches, the coupling fault effect is addressed by diagnosing the hazardous currentflow direction patterns of the TSV bus, and encoding the data bits to avoid those patternsat run-time. Different coding schemes are devised to address both types of TSVcoupling, inductive and capacitive. These approaches are devised to be low overhead,fast, and highly efficient. Empirical simulations are performed with both random andrealistic benchmarks, including PARSEC, to demonstrate the efficacy of the devisedapproaches. All these approaches are also implemented at hardware-level, to have arealistic estimate of the imposed overheads at logic-level. Experimental results showthat these approaches improve the communication reliability over TSV links significantly,with no extra TSV and negligible information redundancy or hardware logicoverhead.Overall, this work provides a rich set of TSV coupling-avoidance techniques, besides anaccurate and fast TSV coupling fault modeling simulation framework, for efficient andeffective design of reliable 3D communication architectures. It helps DFT designers tomore easily design robust TSV links.