Design Methodology of Low Power JPEG2000 Codec Exploiting Dual Voltage Scaling
Yicong Meng, Leibo Liu, Zhang Li, Zhihua Wang · 2006
This paper proposed a novel dual voltage scaling layout architecture and a design methodology of low power JPEG2000 codec exploiting dual voltage scaling. Fabricated in SMIC 0.18μm 1P6M standard CMOS technology, this codec is capable of JPEG2000 compression/decompression with a 1280x1024 pixel (YUV422 full color) at 20frames/s employing 100MHz operation frequency. And the power consumption is 465mW @ 1.8V and 100MH. Applied with dual voltage scaling technique, the power dissipation is reduced by 28.5%.