Formal verification of pipelined and superscalar processors
Toru Shonai, Tsuyoshi Shimizu · 2002
We describe a formal verification algorithm for pipelined and superscalar processors. This algorithm proves the equivalence between a processor's design and its specifications by rewriting recursive functions and using a new type of mathematical induction: extended recursive induction. Partial unfolding makes it possible to derive superscalar specifications from instruction-wise specifications. After the user indicates only selectors in the design, this algorithm can automatically prove correctness. The performance is independent of not only data width but also memory size. Experimental results are also presented.