A bit scalable architecture for fuzzy processors
Roberto d’Amore, Karl Heinz Kienitz, Osamu Saotome · 2003
Several hardware architectures to implement fuzzy processors have been proposed to satisfy real-time requirements, but very few of these are suitable for automatic synthesis. This paper presents bit scalable architecture that allows the automatic synthesis of fuzzy processors in different bit wide resolution. The synthesis is made from a VHDL description. The size of the internal units is defined from a small number of parameters in the highest level entity.