TRANS: a fast and memory-efficient path delay fault simulator
Mneg Chiy Lin, Jwu E. Chen, Chung Len Lee · 2002
For path fault testing, a simulator may suffer from handling an enormous number of paths for their representation and simulation. This paper proposes a fast and memory-efficient path delay fault simulator TRANS. Applied to the ISCAS benchmark circuits, TRANS runs one million patterns within 2.5 hours and 2.2 mega-bytes for each circuit, except for c6288. Comparing the experimental results with those of DAC'89, TRANS achieves 85 times the gain of memory-speed product.>