A novel architecture for CIC decimation filter
B R Sachin, B S Ullas · 2014
Cascaded Integrator Comb (CIC) structure is used extensively in the design of a decimation filter. This paper analyses the existing design of decimation filter and proposes a new design with reduced hardware requirements. The designs are modelled using VHDL, simulated using ISim and implemented in Spartan 3E FPGA. The synthesis report shows the reduction in number of I/O bits.