Viterbi hardware implementation for GSM
Wang Kaiming, Weiling Wu · 2002
The paper presents a novel Viterbi decoder hardware implementation, with the code rate R=1/2 and the constraint length K=5, for the GSM land mobile system. With the use of one XILINX FPGA 3090 chip to replace the ACSs' function, which results in a much simpler hardware and routing structure, this system makes the final ASIC fabrication a very direct consequence.>