Systematic VHDL code generation using pipeline operations produced by high level synthesis
P. Arato, Tibor Kandár · 2004
We present a method for systematic VHDL code generation from a data-flow representation. In such cases, a methodology is needed that yields a hardware description, which are synthetized and mapped into an FPGA. This procedure speeds up the development of the prototype, reduces the time-to-market, and helps the logic and timing simulation.