Generating test patterns for bridge faults in CMOS ICs
Brian Chess, Tracy Larrabee · 2002
We describe a system for generating accurate tests for bridge faults (with or without feedback) in CMOS ICs. We present the Test Guarantee Theorem, which allows for accurate test generation for feedback bridge faults via topological analysis of the feedback-influenced region of the faulted circuit (without the need for any post-test verification or explicit examination of inversion parity). We describe our test pattern generation system's treatment of feedback bridge faults in detail and report on the system's performance.>