A VLSI implementation of the VAX vector architecture
D. Fenwick, J. Redford, Timothy Daryl Stanley, D. Williams · 2002
A single-board implementation of the VAX vector architecture is described. The vector processor can be divided into three separate function units: the vector controller, implemented as a single chip; the arithmetic pipelines, implemented by four pairs of chips; and the load/store unit, implemented by one chip. In addition, the load/store chip controls a 1-MB cache. All three function units can operate independently. The vector coprocessor is designed for use in the VAX 6000 model 400 system. It was implemented using 1.5- mu m custom CMOS and LSI logics sea-of-gates gate array. Peak performance is 90 MFLOPS single precision and 45 MFLOPS double precision. The vector coprocessor achieves speedups between 3 and 40 times the scalar CPU across a range of benchmarks.>