An efficient hardware implementation of H.264 TQ/IQT module
Hassen Loukil, Ahmed Ben Atitallah, Patrice Kadionik, N. Masmoudi · 2010
This paper proposes an efficient hardware architecture for H.264 integer transform, quantization, inverse quantization and integer transform module (TQ/IQT). The TQ/IQT architecture can be used for intra 16×16, intra 4×4 and inter prediction modes. It was described in VHDL and was validated and prototyped using a Altera Stratix II FPGA. The design operates at a maximum frequency of 270 MHz and achieves a throughput from 393 to 1686 Msamples/s depending of the prediction mode, permitting its use in H.264/AVC standard directed to HDTV.