Datapath Verification With SystemC Reference Model
Dongjun Lou, Jingkun Yuan, D Li, C. Jacobs · 2006
Bit-level hardware description language (HDL), such as Verilog or VHDL, has its interior problems to describe complex math formulas in register transaction level (RTL). Its Boolean solutions lead to the necessity of complex controls for math operations, and often result in poor performance for datapath verification. Instead of solving the problem at the bit-level, a method of SystemC reference model (SCRM) is proposed to aid conjunctions of bitvector manipulations in RTL into arithmetic number operations in SystemC, which helps to verify the datapath design automatically. The application experience of SCRM in our digital still camera SoC shows that it is much more efficient and thorough to verify the datapath with the assistance of cycle accurate SystemC models realtimely, than previously manual verification