A single chip solution of dual-gigabit Ethernet over 2.5G SDH/SONET
Jinsong Liu, Depeng Jin, Lieguang Zeng · 2003
Gigabit Ethernet over SDH/SONET is the research and development hotspot for communications. This paper presents a scheme of single chip solving dual gigabit Ethernet over 2.5G SDH/SONET, which can flexibly allocate transmission bandwidth for each gigabit Ethernet according to users' demand. We give a new system structure to implement VC4 virtual concatenation and detail flow control operation in the chip design. Taking into account the self-similarity of Ethernet traffic, we construct an M/D/1 queuing model. Based on this model, the influence of FIFO capacity on loss probability of packets and flow control on network throughput are analyzed. The results show the design has good performance. In addition, the application of the chip is introduced.