Predictive BSIM3v3 modeling for the 0.15-0.18 μm CMOS technology node: a process DOE based approach
Vasanth K. R, Jessica Krick, S. Unnikrishnan, Mahalingam Nandakumar, J.B. Jacobs, P. Ehnis, K. Green, Charles F. Machala, Tom Vrotsos · 2003
An efficient and accurate approach using the BSIM3v3 compact model to support concurrent process technology development and circuit design is presented. The key feature is the ability to generate accurate pre-silicon BSIM3 models for new technologies taking into account process information from existing technologies. Device, circuit and process optimization results are presented.