A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture
Carlo Condo, Pascal Giard, François Leduc-Primeau, Gabi Sarkis, Warren J. Gross · IEEE Transactions on Circuits and Systems I Regular Papers · 2017
Powerful forward error correction (FEC) schemes are used in optical communications to achieve bit-error rates (BERs) below 10-15. These FECs follow one of two approaches: the concatenation of simpler hard-decision codes or the usage of inherently powerful soft-decision codes. The first approach yields lower net coding gains (NCGs), but can usually work at higher code rates and have lower complexity decoders. In this paper, we propose a novel FEC scheme based on a product code and a post-processing technique. It can achieve an NCG of 9.52 dB at a BER of 10-15and 9.96 dB at a BER of 10-18, an error-correction performance that sits between that of current hard-decision and soft-decision FECs. A decoder architecture is designed, tested on field programmable gate array and synthesized in 65-nm CMOS technology: its 162 b/cycle worst-case information throughput can reach 100 Gb/s at the achieved frequency of 616 MHz. Its complexity is shown to be lower than that of hard-decision decoders in literature, and an order of magnitude lower than the estimated complexity of soft-decision decoders.