Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures
Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai · 2006
Many dynamic reconfigurable processors are evolving rapidly that offer fast and run-time reconfiguration. To efficiently utilize run-time reconfiguration, we must consider additional memory access cycles due to reconfiguration. In general, dynamic reconfigurable processors read input data from external memory after reconfiguration and write output data to external memory before the next reconfiguration. To realize high performance, we must schedule tasks considering the total execution cycles that include reconfiguration time and memory access overhead. In this paper, we propose a parameterized reconfigurable processor model (PRP-model) and a task partitioning optimization algorithm for the architecture exploration of multicontext dynamic reconfigurable processors. The proposed task partitioning algorithm corresponds to various dynamic reconfigurable architectures by changing parameters and can realize the evaluation of a lot of reconfigurable architectures. Experimental results showed that the proposed algorithm can quickly find near optimal solutions. Using the proposed algorithm, designers can easily evaluate the performance of various dynamic reconfigurable architectures for specific applications