A new high throughput VLSI architecture for H.264 transform and quantization
Peng Chungan, Dunshan Yu, Xixin Cao, Sheng Shimin · 2007
Hybrid transform and scalar quantization is a key component in ITU-T H.264, and mathematic analysis and decomposition are elaborately made for its hardware implementation, the calculation process is simplified, all time-consuming and hardware expensive multiplication and division are avoided effectively. A new block parallel VLSI architecture mainly containing a 2D direct hybrid transform engine and a full wiring 52-level scalar quantizer is proposed. It is very suitable for pipeline acceleration, and the block throughput rate can reach 156 M/s with one register row inserted, which can satisfy 4096times2304@150 Hz digital video coding in real-time easily, even all macroblocks are predicted with intra_16times16 mode.