High-level design validation using algorithmic debugging
次郎 長沼, T. Ogura, T. Hoshino · 2002
This paper proposes a new environment for high-level LSI design validation using "Algorithmic Debugging" and evaluates its benefits on three significant examples. A design is specified at a high-level using the structured analysis (SA) method and some errors included in SA specifications are efficiently located by answering just a few queries from the debugger. The number of interactions between the designer and the debugger is reduced by a factor of ten to a hundred compared to conventional simulation based validation methodologies. This environment promises to be an important step towards efficient high-level LSI design validation.>