An FPGA implementation of the floating point addition
Chokri Souani, Mariem Abid, Rached Tourki · 2002
Recent algorithms require a great number of arithmetic operations. Some algorithms require adequate precision imposing, the use of a long register for arithmetic operators. In this paper, the authors present a floating point format and its FPGA implementation for the addition operation. This format is different from the IEEE standard format, but is able to satisfy a sufficiently large dynamic of operators with an appropriate precision.