A modified reduced adder graph algorithm for multiplier block minimization in digital filters
Fei Xu, Jiajia Chen, Chip-Hong Chang, Ching Chuen Jong · 2005
In this paper, a Modified Reduced Adder Graph (MRAG) algorithm based on RAG-n has been proposed for efficient implementation of the multiplier block of fixed digital filters. Several improvements over RAG-n have been made with the intent to increase the rate of successful synthesis in the optimal part in order to generate solutions of lower logic complexity. Hamming weight is used in place of adder cost to overcome the limitation on the range of coefficient values due to the use of cost lookup table. A detailed average adder cost and 'computation time analysis of the algorithm is performed. The results demonstrated that MRAG is capable of generating lower adder cost solutions than RAG-n and many other distinguished algorithms.