FPGA implementation of face recognition system using efficient 5/3 2D-lifting scheme
Satish S. Bhairannawar, Rajath Kumar M.P, Varsha Mirji, P S Sindhu · 2016
Face recognition is gaining more importance in today's real world for automated transactions. In this paper, we propose FPGA Implementation of Face Recognition System using Efficient 5/3 2D-Lifting scheme. The database image of FVC-2004 DB3_A is resized to 256×256 pixels. The resized image is convolved with 3×3 Gaussian mask kernelsto remove high frequency edges, which improves matching accuracy. The proposed 5/3 2D-Lift DWT is used to extract LL band features of 128×128 coefficients. Similarly, the test image LL band features are extracted and are compared with LL band features of database image using Euclidean distance classifier for accurate matching. The proposed face recognition architecture is implemented on Virtex5 xc5vlx110-2ff676 board. It is observed that the performance parameters such as area and speed are better compared to existing architectures.