Low-latency hardware-efficient memory-based design for large-order FIR digital filters
Pramod Kumar Meher · 2007
It presents a high-throughput linear systolic array for hardware-efficient memory-based realization of finite impulse response (FIR) filters, using a novel area-time efficient implementation of ROM-based multipliers. A concurrent recursive algorithm is derived for the computation of FIR fitter, and the proposed algorithm is ported further to a two-dimensional (2D) systolic structure for reduced-latency direct-ROM-based realization of large order filters. The proposed 2D structure involves nearly the same hardware as the conventional 1D systolic arrays for FIR filter, but involves significantly less latency compared with the others.