A hierarchical cluster-based model with run-time reconfigurable resource allocation on FPGAs
Amin Yoosefi, Hamid Reza Naji · 2016
Programmability, flexibility and parallel computational capabilities are some of the features making field-programmable-gate-arrays (FPGAs) advantageous over application-specific-integrated-circuits (ASICs). Thanks to the dynamic partial reconfiguration, FPGA provides a virtual hardware resource wherein hardware tasks can swap in and out of the hardware dynamically at runtime. In this paper, we extend the FPGA infrastructure by providing it with a hierarchical cluster-based model similar to multi-core systems. In the proposed model, FPGA is hierarchically clustered into one master node at the top of the system model and several cluster nodes, connected through a dedicated network. To support parallel reconfiguration, each node is provided with a dedicated configuration controller. In addition, a runtime reconfigurable resource allocation approach is proposed. In the proposed approach, reconfigurable resources join and leave clusters at runtime dynamically based on runtime conditions, providing reconfigurable resource sharing.