A general purpose simulation environment for HDL based verification
S. Rajadnya, A. Palnitkar · 2002
With designs becoming increasingly complex, creating a simulation environment has become a very important part of the entire design cycle. The purpose of this paper is to describe a simulation environment which helps in reducing development time and making the simulation environment more flexible. We study a novel method for creating a simulation environment of a proprietary bus architecture (henceforth called PBA). After analyzing the PBA architecture, we decided to have 50,000 transactions in order to cover all the possible test scenarios. Our task was to create 50,000 transactions as a part of the PEA verification environment. We decided to create parametrized tests which can be reused. This method has helped us in reducing development time from six man months to approximately two man months.