VLSI Reed Solomon Decoder Design
G.K. Maki, Patrick A. Owsley, K. Cameron, Jack Venbrux · 1986
A Reed Solomon code is a highly efficient error correcting code that NASA will use in future space communication missions. A VLSI implementation of the decoder is presented that accepts data rates of 80Mbits/second. A total of 7 chips are needed and operate with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field operations per second are achieved with this chip set.