Networks-on-chip and Networks-in-Package for High-Performance SoC Platforms
Kangmin Lee, Se-Joong Lee, Donghyun Kim, Kwanho Kim, Gawon Kim, Joungho Kim, Hoi‐Jun Yoo · 2005
A structured packet-switched networks-on-chip (NoC) is designed and implemented for high-performance heterogeneous SoC design platform. The chip integrates multiprocessors, multiple memories, and other heterogeneous intellectual properties and interconnection with 51mW and 1.6GHz on-chip networks. The NoC adopts a partial activated crossbar, low-energy coding, and low-swing signaling for the power consumption optimization. A network-in-package integrating four NoCs is fabricated in a 676-BGA-type package for larger and scalable systems and demonstrates 2D-image-processing and 3D-graphics applications