A very high efficient input shared buffered packet switch for broadband wireless communications
Krishna Lal Baishnab, A. Nag · 2009
The design of a high speed packet switch has been described here. The switch having 4 inputs and 4 outputs (4 × 4) each of four inputs is further subdivided into additional four input queues. The proposed designed have considered both restricted sharing as well as complete sharing. In restricted sharing a finite threshold is imposed to all queue's length. However on unrestricted sharing one queue can occupy, the free space of others queue under certain conditions and invite starvation for those other queues. Under the restricted sharing we have used different algorithms like fixed threshold, Push-out the delayed packet and dynamic threshold under different loads and buffer's size, delay. The simulation results show that a variety of outcomes based on load, buffer size, and delay.