An efficient division algorithm and its architecture
Sau-Gee Chen, Chieh-Chih Li · 2002
In this work, a fast division algorithm and its time/area efficient architecture is proposed. It achieves the best performance in both area and speed aspects over the existing algorithms and implementations. The proposed architecture basically consists of N simple carry-save adders (CSAs) for bit-serial/serial implementation, and N/sup 2/ CSAs for bit parallel implementation. It finishes an N-bit division in 4N carry-save addition time and the result quotient is in binary representation. In addition, there is no complicated quotient decision circuit. Also a fast algorithm is developed to convert the signed-binary number representation to binary representation.>