A fully-static low power, high performance 64-bit 3-level carry skip adder
S. Turrini, S. Menon · 1994
We present in this paper a fully-static 8.1 ns 300 mW 64-bit adder, part of the integer data path of a complex CPU, designed for low power consumption, high-performance and using a today's available 3.3 V 0.6 /spl mu/m CMOS process.