Montgomery multiplier based on secondary booth encoded algorithm
Xiaodong Yan, Shuguo Li · 2007
This paper describes a high-speed Montgomery multiplier based on pipeline large-scale multiplier. It uses secondary booth encoded algorithm for cutting down the number of partial products and adjusting the data-path to get shorter critical path. An ASIC implementation in 0.18 um CMOS standard cell technology can perform 256-bit modular multiplication in 15 ns under 200 MHz clock frequency. The design can be employed in advanced cryptographic system chips such as RSA or ECC chip.