A 250MHz optimized distributed architecture of 2D 8x8 DCT
Peng Chungan, Xixin Cao, Dunshan Yu, Zhang Xing · 2007
Discrete Cosine Transform (DCT) plays an important role in image and video compression, but computing a two-dimensional (2D) DCT, a large number of multiplications and additions are required in a direct approach. Multiplications, which are the most time-consuming and expensive operations in simple processor, can be completely avoided in our proposed architecture for multiple channel real-time image compression. In this paper, a compressed distributed arithmetic architecture for 2D 8x8 DCT is presented, which offers high speed and small area. The basic architecture consists of a 1D row DCT followed by a transpose register array and another 1D column DCT, in which an 8-input 1D DCT structure only requires 15 adders to build a compressed adder matrix and no ROM is needed. Compared with other architectures available, it has a great improvement on computing speed and reducing area.