The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMs
Nihar R. Mohapatra, Deleep R. Nair, Souvik Mahapatra, V. Ramgopal Rao, S. Shukuri · 2004
The programming performance, cycling endurance and scaling of CHISEL NOR flash EEPROMs is studied for two different (halo and no-halo) channel engineering schemes. Programming speed under identical bias, bias requirements under similar programming time, cycling endurance and drain disturb are compared. The scaling properties of programming time (at a fixed bias), bias (at a fixed programming time) and program/disturb margin are studied as cell floating gate length is scaled. The relative merits of these channel engineering schemes are discussed from the viewpoint of futuristic CHISEL cell design.