Matrix based signal processing on a reconfigurable hardware accelerator
M. Otte, Jürgen Götze, M. Bucker · 2005
In this paper we describe a novel architecture for high speed signal processing applications. The respective hardware accelerator is designed to support a certain class of algorithms. The chosen class is based on a special kind of matrix transformation that could be efficiently implemented in terms of CORDIC modules. A consistent notation is presented to ease the process of mapping signal processing algorithms to the considered hardware. It is also shown how to implement complex valued arithmetic with less growth of complexity compared to standard techniques. Some algorithms are examined to illustrate the potential of our approach.