Design of FFT processor with low power complex mutliplier for OFDM-based high-speed wireless applications
Miu Jiang, Bing Yang, Yiling Fu, Anping Jiang, Yin-an Wang, Xuewen Gan, Baoying Zhao, Tiarryi Zhang · 2005
We introduce a fixed-point 16-bit 64-point FFT processor for OFDM-based wireless applications. The processor is based on decimation-in-time (DIT) radix-2 butterfly FFT algorithm. The canonical signed digit is used to implement constant complex multiplications with carry save add (CSA) tree for lower power and cost. The simulation shows the module can reach low cost/power and high speed for OFDM-based high-speed wireless applications.