Performance characteristics of a 5 Gbps functional test module
Al-Hussein Maysir Majid, David C. Keezer, N. Taher, C. Gray, J. Ahmad · 2005
This paper describes a research project that develops new low-cost techniques for testing wafer-level packaged (WLP) devices using a miniature test module connected to the top of a wafer probe card with multiple high-speed (2-5 Gbps) signals. The project uses commercially available components to keep costs low, yet achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. A CMOS FPGA-based logic core provides flexibility, adaptability, and communication with controlling computers while positive emitter-coupled logic (PECL) achieves multi-gigahertz data rates with about +25 ps timing accuracy. Multi-gigahertz signals are generated with a rise time in the order of 150 ps and exhibit low jitter /spl sim/50 ps. Several programmable delay chips are used to obtain 10ns range and 10 ps resolution for adjusting critical timing signals. However, programming of these delay chips is complicated by inherent non-linearities. Currently research is under progress to calibrate these timing errors.