I/sub DDQ/ testing of a 180 MHz HP PA-RISC microprocessor with redundancy programmed caches
Tom Meneghini, D.D. Josephson · 2002
The Hewlett-Packard PA7300LC is a 180 MHz PA-RISC microprocessor consisting of 1.2 million core logic transistors and 8 million cache transistors. The design of the power distribution network for this chip allowed independent measurement of the I/sub DDQ/ current for both the cache and the core logic of the chip. A test method was developed whereby it was possible to distinguish cache I/sub DDQ/ data resulting from a cache that was free from defects or was repaired through redundancy programming. The authors collected I/sub DDQ/ data from over fifty thousand parts and an analysis of this data is presented along with some conclusions.