Low power spread spectrum code generator based on parallel shift register implementation
Menahem Lowy · 2002
This paper describes a very low-power Gold code generator based on a parallel implementation of linear feedback shift registers. The parallel architecture dissipates less power than the conventional serial architecture and also allows a higher throughput rate. The parallel architecture and its associated switch minimization algorithm are explained and the architecture of the code generator is described. The Gold code generator designed in a 2 micron CMOS technology consumes less than 1000 microwatts when clocked at 50 MHz.