Thermal, power, and performance shaping of multicore floorplans
Fadi N. Sibai · 2010
In this paper, we explore and evaluate multicore processor architecture and floorplans in light of performance, power, and thermal issues. Cores-out-caches-inside and both interleaved and non-interleaved versions of cores-sandwiched-between-caches approaches are considered, with 3 levels of cache memories and ring and bus-based interconnects.