On-Line Test Vector Generation from Temporal Constraints Written in PSL
Yann Oddos, Katell Morin-Allory, D. Borrione · 2006
We propose an efficient solution to automatically generate test vectors that satisfy an assumed property written in PSL. From a "foundation language" formula, we build a synthesizable generator that produces random temporal test vectors compliant with the formula. Generators are space and speed efficient when synthesized on FPGA, and their connection to the device under test is a portable solution across verification platforms for simulation and emulation